1. Field of the Invention
This invention relates to interconnects formed in semiconductor devices, and more particularly to copper interconnects formed in Inter-Metallic Dielectric (IMD) layers.
2. Description of Related Art
As semiconductor device dimensions are constantly being scaled down to the deep submicron regime, the current metallization scheme requires revision.
U.S. Pat. No. 5,674,787 of Zhao et al. for "Selective Electroless Copper Deposited Interconnect Plugs for ULSI Applications" shows selective Cu electroless deposition in a via trench hole using a seed layer. An electroless copper deposition method selectively forms encapsulated copper plugs to connect conductive regions of a semiconductor device. A contact displacement technique forms a thin activation copper layer on a barrier metal layer, e.g. TiN, which is present as a covering layer on an underlying metal layer. Copper is deposited in the via by an electroless auto-catalytic process. Electroless copper deposition continues until the via is almost filled which leaves sufficient room at the top for an upper encapsulation to be formed there, but first the device is rinsed in DI (deionized) water to remove the electroless deposition solution. Then after the rising away of the electroless copper solution, a cap barrier layer, from 500 .ANG. to about 1500 .ANG. thick, is formed of a variety of metals or metal alloys such as Ni, Co, Ni--Co alloy, CoP, NiCoP, or NiP from another electroless solution. The bottom barrier layer and the cap barrier layer complete the full encapsulation of the copper plug via.
U.S. Pat. No. 5,470,789 of Misawa for "Process for Fabricating Integrated Circuit Devices" produces a TiN/Cu interconnect having a capping layer formed of TiN unlike the copper alloy metal cap layer of this invention.